1. Field of the Invention
This invention relates to the field of random access memories, and in particular to a low power static random access memory SRAM.
2. Description of Related Art
In a computer, two types of main memory can be used to provide random access circuits, namely static random-access memory (SRAM) and dynamic random-access memory (DRAM). A single memory chip is made up of several million memory cells. In a SRAM chip, each memory cell typically consists of a single flip-flop (for storing the binary digits 1 or 0) and several transistors for the reading and writing operations. The access time of an SRAM chip is faster than a DRAM chip. SRAM chips are typically used in cache memory.
Current mode SRAMs designs, as the name would suggest, perform read-write operations in current mode during read and write operations and therefore consume less power than voltage mode devices.
Designers of prior art current mode SRAM architectures and implementations have traditionally focused on high speed, low power and low-voltage. Examples of such current-mode architectures are found in Wang et al., Low-Power Embedded SRAM Macros with Current-Mode Read/Write Operations, Proceedings ISLPED98, which purports to disclose a fully current-mode SRAM that uses 30% less power than an SRAM with only current-mode read operation; Khellah and Elmasry, Circuit techniques for High-Speed and Low-Power Multi-Port SRAMs, 1998 IEEE; and Wang and Lee, A New Current-Mode Sense Amplifier for Low-Voltage Low-Power SRAM Design, 1998 IEEE. The contents of these papers are incorporated herein by reference.
However, such designs use separate bitlines for read and write in combination with current mode read bitlines and are not capable of offering ultra low power consumption.